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hm628128a series 131,072-word 8-bit high speed cmos static ram rev. x january 1995 the hitachi hm628128a is a cmos static ram organized 128 kword 8 bit. it realizes higher density, higher performance and low power consumption by employing 0.8 ? hi-cmos process technology. it offers low power standby power dissipation; therefore, it is suitable for battery back-up systems. the device, packaged in a 525-mil sop (460-mil body sop) or a 600-mil plastic dip, or a 8 20 mm tsop with thickness of 1.2 mm, is available for high density mounting. tsop package is suitable for cards, and reverse type tsop is also provided. features high speed fast access time: 55/70/85/100 ns (max) low power active: 75 mw (typ) standby: 10 ? (typ) single 5 v supply completely static memory no clock or timing strobe required equal access and cycle times common data input and output three state output directly ttl compatible all inputs and outputs capability of battery back up operation 2 chip selection for battery back up ade-xxx-xxx
ordering information access type no. time package hm628128alp? 55 ns 600-mil 32-pin hm628128alp? 70 ns plastic dip hm628128alp? 85 ns (dp-32) hm628128alp?0 100 ns hm628128alp?l 55 ns hm628128alp?l 70 ns hm628128alp?l 85 ns hm628128alp?0l 100 ns hm628128alp?sl 55 ns hm628128alp?sl 70 ns hm628128alp?sl 85 ns hm628128alp?0sl 100 ns hm628128alfp? 55 ns 525-mil 32-pin hm628128alfp? 70 ns plastic sop hm628128alfp? 85 ns (fp-32d) hm628128alfp?0 100 ns hm628128alfp?l 55 ns hm628128alfp?l 70 ns hm628128alfp?l 85 ns hm628128alfp?0l 100 ns hm628128alfp?sl 55 ns hm628128alfp?sl 70 ns hm628128alfp?sl 85 ns hm628128alfp?0sl 100 ns access type no. time package hm628128alt? 55 ns 8 mm 20 mm hm628128alt? 70 ns 32-pin tsop hm628128alt? 85 ns (normal type) hm628128alt?0 100 ns (tfp-32d) hm628128alt?l 55 ns hm628128alt?l 70 ns hm628128alt?l 85 ns hm628128alt?0l 100 ns hm628128alt-5sl 55 ns hm628128alt-7sl 70 ns hm628128alt-8sl 85 ns hm628128alt-10sl 100 ns hm628128alr? 55 ns 8 mm 20 mm hm628128alr? 70 ns 32-pin tsop hm628128alr? 85 ns (reverse type) hm628128alr?0 100 ns (tfp-32dr) hm628128alr?l 55 ns hm628128alr?l 70 ns hm628128alr?l 85 ns hm628128alr?0l 100 ns hm628128alr-5sl 55 ns hm628128alr-7sl 70 ns hm628128alr-8sl 85 ns hm628128alr-10sl 100 ns 2 hm628128a series
pin arrangement 3 hm628128a series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 cs2 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 cc (top view) hm628128alp/alfp series 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a4 a5 a6 a7 a12 a14 a16 nc v a15 cs2 we a13 a8 a9 a11 ss a3 a2 a1 a0 i/o0 i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 i/o7 cs1 a10 oe cc (top view) hm628128alt series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we cs2 a15 v nc a16 a14 a12 a7 a6 a5 a4 ss oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 a3 cc (top view) hm628128alr series pin description pin name function a0 ?a16 address i/o0 ?i/o7 input/output cs1 chip select 1 cs2 chip select 2 we write enable pin name function oe output enable nc no connection v cc power supply v ss ground
block diagram function table cs1 cs2 oe we mode v cc current i/o pin ref. cycle h x x x standby i sb , i sb1 high-z x l x x standby i sb , i sb1 high-z l h h h output disable i cc high-z l h l h read i cc dout read cycle l h h l write i cc din write cycle (1) l h l l write i cc din write cycle (2) note: x: h or l 4 hm628128a series ? ? ? ? ? ? ? ? ? ? ? i/o0 i/o7 cs2 we oe a8 a9 a11 a0 a2 v v cc ss row decoder memory matrix 512 x 2,048 column i/o column decoder input data control timing pulse generator read/write control a1 a3 a13 a15 a6 a7 a12 a14 a16 a5 a4 cs1 a10 (msb) (lsb) (lsb) (msb)
absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ?.5 to +7.0 v voltage on any pin relative to v ss *1 v t ?.5 *2 to v cc + 0.3 *3 v power dissipation p t 1.0 w operating temperature topr 0 to +70 ? storage temperature tstg ?5 to +125 ? storage temperature under bias tbias ?0 to +85 ? note: 1. with respect to v ss 2. ?.0 v for pulse half-width 30 ns 3. maximum voltage is 7.0v. recommended dc operating conditions (ta = 0 to +70?) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input voltage v ih 2.2 v cc + 0.3 v (hm628128a-7/8/10) v il ?.3 *1 0.8 v input voltage v ih 2.4 v cc + 0.3 v (hm628128a-5) v il ?.3 *1 0.8 v note: 1. ?.0 v for pulse half-width 30 ns 5 hm628128a series
dc characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) parameter symbol min typ *1 max unit test conditions input leakage current |i li | 1.0 ? vin = v ss to v cc output leakage current |i lo | 1.0 ? cs1 = v ih or cs2 = v il or oe = v ih or we = v il , v i/o = v ss to v cc operating power supply i cc ?530ma cs1 = v il , cs2 = v ih , current: dc others = v ih /v il i i/o = 0 ma operating power supply i cc1 45 70 ma min cycle, duty = 100%, current (hm628128 cs1 = v il , cs2 = v ih , a-7/8/10) others = v ih /v il i cc1 ?080ma i i/o = 0 ma (hm628128 a-5) i cc2 15 25 ma cycle time = 1 ?, duty = 100%, i i/o = 0 ma, cs1 0.2 v, cs2 3 v cc ?0.2 v v ih 3 v cc ?0.2 v, v il 0.2 v standby power supply i sb 1 2 ma (1) cs1 = v ih , cs2 = v ih or current: dc (2) cs2 = v il standby power supply i sb1 2 100 ? 0 v vin v cc , current (1): dc (l version) (1) cs1 3 v cc ?0.2 v, i sb1 ? 50a cs2 3 v cc ?0.2 v or (l-l/l-sl (2) 0 v cs2 0.2 v version) output voltage v ol 0.4 v i ol = 2.1 ma v oh 2.4 v i oh = ?.0 ma note: 1. typical values are at v cc = 5.0 v, ta = +25? and specified loading. capacitance (ta = 25?, f = 1.0 mhz) *1 parameter symbol min typ max unit test conditions input capacitance cin 8 pf vin = 0 v input/output capacitance c i/o 10 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested. 6 hm628128a series
ac characteristics (ta = 0 to +70?, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0.8 v to 2.4 v (hm628128a-7/8/10) 0 v to 3 v (hm628128a-5) input rise and fall times: 5 ns input and output timing reference levels: 1.5 v output load: 1 ttl gate and cl (100 pf) (hm628128a-7/8/10) 1 ttl gate and cl (30 pf) (hm628128a-5) (including scope & jig) read cycle hm628128a -5 -7 -8 -10 parameter symbol min max min max min max min max unit notes read cycle time t rc 55 70 85 100 ns address access time t aa 55 70 85 100 ns chip selection to t co1 55 70 85 100 ns output valid t co2 55 70 85 100 ns output enable to t oe 30 35 45 50 ns output valid chip selection to t lz1 5 10 10 10 ns 2, 3 output in low-z t lz2 5 10 10 10 ns 2, 3 output enable to t olz 5 5 5 5 ns 2, 3 output in low-z chip deselection to t hz1 0 20 0 25 0 30 0 35 ns 1, 2, 3 output in high-z t hz2 0 20 0 25 0 30 0 35 ns 1, 2, 3 output disable to t ohz 0 20 0 25 0 30 0 35 ns 1, 2, 3 output in high-z output hold from t oh 5 10 10 10 ns address change 7 hm628128a series
read timing waveform *4 notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. at any given temperature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 3. this parameter is sampled and not 100% tested. 4. we is high for read cycle. 8 hm628128a series t t t t t t rc aa co1 lz1 oe olz t hz2 t ohz data valid address cs1 oe dout t oh cs2 address valid t co2 t lz2 high impedance t hz1
write cycle hm628128a -5 -7 -8 -10 parameter symbol min max min max min max min max unit notes write cycle time t wc 55 70 85 100 ns chip selection to t cw 50 60 75 80 ns end of write address setup time t as 0000ns address valid to t aw 50 60 75 80 ns end of write write pulse width t wp 40 50 55 60 ns write recovery time t wr 0000ns write to output in t whz 0 20 0 25 0 30 0 35 ns 10 high-z data to write time t dw 25 30 35 40 ns overlap data hold from t dh 0000ns write time output active from t ow 5555ns10 end of write 9 hm628128a series
write timing waveform (1) ( oe clock) 10 hm628128a series address cs1 we dout din t wc t cw t wr t wp t ohz t dw t dh *5 *1 *6 *4 address valid t aw cs2 t as high impedance data valid oe *3 *2
write timing waveform (2) ( oe low fixed) notes: 1. a write occurs during the overlap of a low cs1 , a high cs2, and a low we . a write begins at the latest transition among cs1 going low, cs2 going high, and we going low. a write ends at the earliest transition among cs1 going high, cs2 going low, and we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of cs1 going low or cs2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the earliest of cs1 or we going high or cs2 going low to the end of write cycle. 5. during this period, i/o pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 6. if the cs1 goes low simultaneously with we going low or after the we going low, the outputs remain in a high impedance state. 7. dout is the same phase of the latest written data in this write cycle. 8. dout is the read data of next address. 9. if cs1 is low and cs2 high during this period, i/o pins are in the output state. therefore, the input signals of opposite phase to the outputs must not be applied to them. 10. this parameter is sampled and not 100% tested. 11. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of 11 hm628128a series address cs1 we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *9 *7 *8 *5 *1 *11 *6 *4 address valid data valid cs2 *2 *3 high impedance
data bus contention. t wp 3 t dw min + t whz max low v cc data retention characteristics (ta = 0 to +70?) parameter symbol min typ max unit test conditions *4 v cc for data retention v dr 2.0 v cs1 3 v cc ?0.2 v, cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v vin>0 v data retention current i ccdr ? 50 *1 ? v cc = 3.0 v, vin 3 0 v (l version) cs1 3 v cc ?0.2v i ccdr ? 30 *2 ? cs2 3 v cc ?0.2 v or (l-l version) 0 v cs2 0.2 v i ccdr ? 15 *3 ? (l-sl version) chip deselect to t cdr 0 ns see retention waveform data retention time operation recovery time t r 5ms low v cc data retention timing waveform (1) ( cs1 controlled) low v cc data retention timing waveform (2) (cs2 controlled) 12 hm628128a series cc v 4.5 v 2.2 v 0 v cs1 t cdr t r cs1 v ?0.2 v cc dr1 v data retention mode > cc v 4.5 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr2 v data retention mode 0.4 v t < <
notes: 1. 20 ? max at ta = 0 to 40?c (l-version). 2. 6 ? max at ta = 0 to 40?c (l-l-version). 3. 3 ? max at ta = 0 to 40?c (l-sl-version). 4. cs2 controls address buffer, we buffer, cs1 buffer, oe buffer, and din buffer. if cs2 controls data retention mode, vin levels (address, we , oe , cs1 , i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v. the other input levels (address, we , oe , i/o) can be in the high impedance state. 13 hm628128a series

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